usage: qas [-h] [-m MEM_MAP_FILE] [--object OBJECT_FILE] [-v VH_FILE] [--verilog_entity ENTITY_NAME] [-o OUTPUT_FILE] [-p OUTPUT_FILE] [-I PATH [PATH ...]] 
[-D MACRO [MACRO ...]] SOURCE_FILE [SOURCE_FILE ...]

A reference implementation of a relocating assembler for QCPU ISA.

positional arguments:
SOURCE_FILE           Source files to be assembled.

options:
-h, --help              show this help message and exit
-m, --memory_map MEM_MAP_FILE
                        Render memory map and output it to the specified text file.
--object OBJECT_FILE  Output object file instead of linked binary. If this argument is supplied, "--output" argument is ignored.
-v, --verilog VH_FILE
                        Output Verilog header file. If this argument is supplied, qas will additionally produce bytecode rendered as Verilog header file.
--verilog_entity ENTITY_NAME
                        Specifies name of array that is used in '--verilog' parameter output (default 'memory')
-o, --output OUTPUT_FILE
                        Specifies the output binary file.
-p, --preprocess OUTPUT_FILE
                        Preprocess input files and output result to a specified file. If this option is used, no further actions will be performed.
-I, --include PATH [PATH ...]
                        Adds a path to the list of paths assembler is looking into while processing includes.
-D, --define MACRO [MACRO ...]
                        Defines a global macro. Can be overridden by `#define` statements in code. Format is MACRO_NAME=MACRO_CONTENTS, e.g. FOO=42.