The Q CPU: Instruction Set Architecture
Instruction format
QCPU instruction always consists of 4 bytes (32 bits).
1st (MSB) byte is an opcode: 3 bits that specify flavour plus 5 bits that specify instruction. E.g., an ADDI is 0x21: 0x2 (I flavour) + 0x1 (ADD instruction).
3 remaining bytes contain operands.
Flavours
Each instruction can be used in one or several flavours, i. e. addressing modes depending on what is to be used as instruction arguments.
Available flavours are:
-
A: a register index and a 20-bit memory reference; -
E: one register index; -
F: two register indices; -
I: two register indices and a 16-bit imediate value; -
Q: a 24-bit immediate value; -
R: three register indices; -
S: a register index and a 20-bit immediate value; -
N: no arguments.
Instructions
NOP 0x00
Flavours: N (0x00)
Arguments: None.
Description: Does nothing.
ADD 0x01
Flavours: R (0x21), I (0x41)
Arguments: Destination, operand 1, operand 2.
Description: ADDs operands (destination = operand 1 + operand 2).
SUB 0x02
Flavours: R (0x22), I (0x42)
Arguments: Destination, operand 1, operand 2.
Description: SUBtracts operands (destination = operand 1 - operand 2).
AND 0x03
Flavours: R (0x23), I (0x43)
Arguments: Destination, operand 1, operand 2.
Description: Bitwise AND of operands (destination = operand 1 & operand 2).
OR 0x04
Flavours: R (0x24), I (0x44)
Arguments: Destination, operand 1, operand 2.
Description: Bitwise OR of operands (destination = operand 1 | operand 2).
XOR 0x05
Flavours: R (0x25), I (0x45)
Arguments: Destination, operand 1, operand 2.
Description: Bitwise XOR of operands (destination = operand 1 ^ operand 2).
LSH 0x06
Flavours: S (0x66)
Arguments: Destination, operand 1.
Description: SHifts destination Left by "operand 1" bits. (destination = destination << operand 1).
RSH 0x07
Flavours: S (0x67)
Arguments: Destination, operand 1.
Description: SHifts destination Right by "operand 1" bits. (destination = destination >> operand 1).
NOT 0x08
Flavours: F (0xA8)
Arguments: Destination, operand 1.
Description: Bitwise NOT of operand. (destination = ~operand 1).
LD 0x09
Flavours: S (0x69), F (0xA9), A (0xE9)
Arguments: Destination, operand 1.
Description: STores operand in the destination. Accepts memory offsets as operand references. (destination = operand).
ST 0x0A
Flavours: F (0xAA), A (0xEA)
Arguments: Source, operand 1.
Description: STores source in destination referenced by the operand. Accepts memory offsets as operand references. (operand = source).
BEQ 0x0B
Flavours: R (0x2B), I (0x4B)
Arguments: Address ref, operand 1, operand 2.
Description: Branches to (loads into PC) address reference if operand 1 is EQual to operand 2 (PC = addr, operand 1 == operand 2).
BNE 0x0C
Flavours: R (0x2C), I (0x4C)
Arguments: Address ref, operand 1, operand 2.
Description: Branches to (loads into PC) address reference if operand 1 is Not Equal to operand 2 (PC = addr, operand 1 != operand 2).
BGT 0x0D
Flavours: R (0x2D), I (0x4D)
Arguments: Address ref, operand 1, operand 2.
Description: Branches to (loads into PC) address reference if operand 1 is Greater Than operand 2 (PC = addr, operand 1 > operand 2).
BLT 0x0E
Flavours: R (0x2E), I (0x4E)
Arguments: Address ref, operand 1, operand 2.
Description: Branches to (loads into PC) address reference if operand 1 is Lesser Than operand 2 (PC = addr, operand 1 < operand 2).
JMP 0x0F
Flavours: F (0xCF), Q (0x8F)
Arguments: Address ref.
Description: Unconditional JuMP to address ref (PC = addr).
JAL 0x10
Flavours: F (0xD0), Q (0x90)
Arguments: Address ref.
Description: Jump And Link: puts current PC on the stack, increments SC, loads address ref to PC (PC -> stack && SC++ && PC = addr).
RET 0x11
Flavours: N (0x11)
Arguments: None.
Description: RETurn: loads value on top of the stack into PC, decrements SC (PC <- stack && SC—).
PSH 0x12
Flavours: Q (0x92), E (0xD2)
Arguments: Operand 1.
Description: PuSH: pushes value onto stack, increments SC (operand 1 -> stack && SC++).
POP 0x13
Flavours: E (0xD3)
Arguments: Destination.
Description: POPs value from stack into destination, decrements SC (destination <- stack && SC—).
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